Logic Gate Circuit Generator
Draw the logic gate circuit for a Boolean expression: as written, as a minimal AND–OR or OR–AND circuit, or with NAND or NOR gates only. Built gate by gate with steps, checked on every input, and downloadable as SVG.
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Variables are a letter with optional digits (A, b, x1). NOT: A' !A ¬A ~A · AND: AB A·B A*B A&B A∧B · OR: A+B A|B A∨B · XOR: A^B A⊕B · implies: -> → · if and only if: <-> ↔ · constants 0 and 1. You can also enter a list such as Σm(1, 3, 5) + d(7), ΠM(0, 2) or F(A, B, C) = Σm(1, 3).
How to draw a circuit from an expression
- Type the expression, for example
A'B + AC. - Choose how to draw it: As written follows your expression exactly; Minimal SOP and Minimal POS use the fewest gates in two levels; NAND only and NOR only use a single gate type, as on many real chips.
- Press Draw circuit. The finished circuit appears first, then Next step builds it gate by gate, highlighting the gates added at each step.
Reading the drawing
Each input variable is a vertical line on the left. A dot shows where a wire takes its value from that line; wires that cross without a dot are not connected. Gates are named G1, G2… in the order they are built, and the output on the right is F. The drawing is checked against your expression on every row of the truth table.
NAND-only and NOR-only circuits
NAND and NOR are universal gates: any circuit can be built from just one of them. Starting from the minimal sum of products, double negation and De Morgan's law turn an AND–OR circuit into a NAND–NAND circuit with the same layout: every AND becomes a NAND and the final OR becomes a NAND. A NAND with both inputs tied together is an inverter. NOR-only circuits are built the same way from the minimal product of sums.
Frequently asked questions
How is the circuit counted?
The tool shows the number of gates, the number of gate inputs (a common cost measure) and the number of levels (gate delays from input to output). Inverters on the inputs count as gates.
How are → and ↔ drawn?
There is no implication gate, so A → B is drawn as ¬A ∨ B. A ↔ B is drawn as an XNOR gate, and ⊕ as an XOR gate.
Can I use the drawing elsewhere?
Download SVG saves a vector image that stays sharp at any size, for reports and slides.
Is there a size limit?
Up to 10 variables, and drawings up to 80 gates. For larger expressions, try the minimal SOP or POS drawing, which usually needs far fewer gates.